خلاصة:
The evolution of today's application technologies requires a certain level of robustness, reliability and ease of integration. We choose the Fields Programmable Gate Array (FPGA) hardware description language to implement the facial recognition algorithm based on "Eigen faces" using Principal Component Analysis. In this paper, we first present an overview of the PCA used for facial recognition, then use a VHSIC Hardware Description Language (VHDL) simulation and design platform, which is the ISE. We describe the operation of each block and implement, thereafter, the computation of the global centered images. This corresponds to the first step of the PCA algorithm to assess its performance. The comparison of the results of this implementation with that of MATLAB confirmed the operability and effectiveness of this method for centralizing images. We also implemented the last part of this algorithm which is the computation of the Manhattan distance. The tests have given very satisfactory results.
ملخص الجهاز:
Implementation of Face Recognition Algorithm on Fields Programmable Gate Array Card Fatima Zohra Allam Signal and Communication Laboratory, Department of Electronics, National Polytechnic School, Algeria.
We choose the Fields Programmable Gate Array (FPGA) hardware description language to implement the facial recognition algorithm based on "Eigen faces" using Principal Component Analysis.
In this paper, we first present an overview of the PCA used for facial recognition, then use a VHSIC Hardware Description Language (VHDL) simulation and design platform, which is the ISE.
, 2006), (Deschamps & Bioul, 2006) and (Pistorius & Hutton, 2003).
The VHDL is a development tool that transforms said description into a file that can be configured in four main steps (Betz & Rose, 1997), (Chen & Chang, 2017) and (Tang et al.
Algorithm of the decision phase In what follows, we will explain the blocks that will be implemented on the FPGA card Algorithm for Computing Centered Images The centered images are computed from the database stored in the ROM.
Algorithm for computing centered images on ISE The circuit has four identical input signals and eight identical output signals: The "RESET" input resets the different modules.
Schematic representation of a centered image computation block RTL Analysis RTL analysis transforms VHDL language into logic gates (Dossis, 2011) and (Lyalin, 2007).
, 2016), (Das & Chatterji, 1990) and (Melter, 1991) and (Yuhui et al.
Simulation results for the Manhattan distance computation {مراجعه شود به فایل جدول الحاقی} Conclusion In this paper, we presented the results of our contribution to the FPGA implementation of the PCA algorithm for facial recognition.